Tunable Analog and Reconfigurable Digital Circuits with Nanoscale DG - MOSFETs 9

1.1 CMOS downscaling to DG-MOSFETs As device scaling aggressively continues down to sub-32nm scale, MOSFETs built on Silicon on Insulator (SOI) substrates with ultra-thin channels and precisely engineered source/drain contacts are required to replace conventional bulk devices (Celler & Cristoloveanu, 2009). Such SOI MOSFETs are built on top of an insulation (SiO2) layer, reducing the coupling capacitance between the channel and the substrate as compared to the bulk CMOS. The other advantages of an SOI MOSFET include higher current drive and higher speed, since doping-free channels lead to higher carrier mobility. Additionally, the thin body minimizes the current leakage from the source to drain as well as to the substrate, which makes the SOI MOSFET a highly desirable device applicable for high-speed and low-power applications. However, even these redeeming features are not expected to provide extended lifetime for the conventional MOSFET scaling below 22nm and more dramatic changes to device geometry, gate electrostatics and channel material are required. Such extensive changes are best introduced gradually, however, especially when it comes to new materials. It is the focus on 3D transistor geometry and electrostatic design, rather than novel materials, that make the multi-gate MOSFETs as one of the most suitable candidates for the next phase of evolution in Si MOSFET technology (Skotnicki et al., 2005; Amara & Olivier, 2009). The multi-gate MOSFET architectures can efficiently control the channel from multiple sides of the channel instead of the top-side in planar bulk MOSFETs. The ability to alter channel potential by multiple gates (i.e double, triple, surround) provides a relatively easier and robust way to control the channel electrostatics, reducing the short channel effects and leakage concerns considerably. Thus, the last decade has witnessed a frenzy of design activity to evaluate, compare and optimize various multi-gate geometries, mostly from the digital CMOS viewpoint (Skotnicki et al., 2005). While this effort is still ongoing, the purpose of the present chapter is to underline and exemplify the massive increase in the headroom for CMOS nanocircuit engineering, especially at themixed-signal systems, when the conventional MOSFET architecture is augmented with one extra gate. Being the simpler and relatively easier to fabricate among the multigate MOSFET structures (FinFET, MIGFet,Π-MOSFET and so on) the double gate (DG) MOSFET is chosen here to explore these new circuit possibilities. Tunable Analog and Reconfigurable Digital Circuits with Nanoscale DG-MOSFETs 9